There will not be a large penalty for turning in Lab-2 a week late, so if you are stuck, do not panic. If you can do it on time and want a grade of 100%, please do so.
I will provide help on the Web site, by email, and in class on Friday.
I realize now that your last work on VHDL did not involve different modules. The fact that the non-pipelined VHDL model has different modules makes Lab-2 much easier to do. We simply have to design four Delay Modules and insert them between the modules for the five stages.
The first Pipeline Register (delay module) shown by the red
line, IF_ID ,separates the IF stage from the next stage (ID).
We are going to break two Signals (wires): the PC+4 and the Instruction signals. We need an input for each of these, and an output that will reflect the input values at the instant of time when the clock (Event) changes from positive to negative. The VHDL code for Entity "Ifid" is created in the text file "IFID.VHD" which contains:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY Ifid IS PORT ( Instruction_out: OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 ); Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 ); PC_plus_4_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ); PC_plus_4 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); clock, reset : IN STD_LOGIC); END Ifid; ARCHITECTURE behavior OF Ifid IS BEGIN PROCESS BEGIN WAIT UNTIL ( clock'EVENT ) AND ( clock = '1' ); IF reset = '1' THEN Instruction_out <= "00000000000000000000000000000000"; PC_plus_4_out <= "00000000"; ELSE Instruction_out <= Instruction; PC_plus_4_out <= PC_plus_4; END IF; END PROCESS; END behavior;
This is a "behavioral" description rather than a gate-level description. If Signal "reset" is one at the rising clock edge, the output lines are all zeroes. Otherwise the input values get transferred to the outputs. We will need to create new Signals (lines or wires) to connect the Instruction output on the Instruction Register (not to be confused with the Signal named "Instruction" that was connected there, but will now be connected to "Instruction_out" on the new module.
The changes to TOP-SPIM.VHD are shown below in red:
-- Top Level Structural Model, TOP_SPIM
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY TOP_SPIM IS
PORT( reset, clock : IN STD_LOGIC;
-- Output important signals to pins for easy display in Simulator
PC, ALU_result_out, read_data_1_out,
read_data_2_out, write_data_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Instruction_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Branch_out, Zero_out, Memwrite_out,
Regwrite_out : OUT STD_LOGIC );
END TOP_SPIM;
ARCHITECTURE structure OF TOP_SPIM IS
COMPONENT Ifetch
PORT( Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_plus_4_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Add_result : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Branch : IN STD_LOGIC;
Zero : IN STD_LOGIC;
PC_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
clock,reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT Ifid -- new component defined. Copy from file IFID.VHD
PORT ( Instruction_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_plus_4_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_plus_4 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
clock, reset : IN STD_LOGIC);
END COMPONENT;
COMPONENT Idecode
PORT( read_data_1 : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
read_data_2 : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
ALU_result : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
RegWrite, MemtoReg : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
Sign_extend : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END COMPONENT;
* * *
-- declare signals used to connect VHDL components
SIGNAL PC_plus_4 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL PC_plus_4_if : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); -- new Signal defined.
SIGNAL read_data_1 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL read_data_2 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Sign_Extend : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Add_result : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL ALU_result : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL read_data : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL ALUSrc : STD_LOGIC;
SIGNAL Branch : STD_LOGIC;
SIGNAL RegDst : STD_LOGIC;
SIGNAL Regwrite : STD_LOGIC;
SIGNAL Zero : STD_LOGIC;
SIGNAL MemWrite : STD_LOGIC;
SIGNAL MemtoReg : STD_LOGIC;
SIGNAL MemRead : STD_LOGIC;
SIGNAL ALUop : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
SIGNAL Instruction : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL Instruction_if : STD_LOGIC_VECTOR( 31 DOWNTO 0 ); -- new Signal defined.
BEGIN
* * *
-- copy important signals to output pins for easy
-- display in Simulator
Instruction_out <= Instruction;
ALU_result_out <= ALU_result;
read_data_1_out <= read_data_1;
read_data_2_out <= read_data_2;
write_data_out <= read_data WHEN MemtoReg = '1' ELSE ALU_result;
Branch_out <= Branch;
Zero_out <= Zero;
RegWrite_out <= RegWrite;
MemWrite_out <= MemWrite;
-- connect the 5 MIPS components
IFE : Ifetch
PORT MAP ( Instruction => Instruction_if, -- originally to Instruction
PC_plus_4_out => PC_plus_4_if, -- originally to PC_plus_4
Add_result => Add_result,
Branch => Branch,
Zero => Zero,
PC_out => PC,
clock => clock,
reset => reset );
IDF : Ifid
PORT MAP ( Instruction => Instruction_if, -- the Input "Instruction" from Instruction_if
PC_plus_4 => PC_plus_4_if,
Instruction_out => Instruction, -- the new module now drives Signal Instruction
PC_plus_4_out => PC_plus_4, -- the new module now drives PC_plus_4
clock => clock,
reset => reset );
ID : Idecode
PORT MAP ( read_data_1 => read_data_1,
read_data_2 => read_data_2,
Instruction => Instruction,
read_data => read_data,
ALU_result => ALU_result,
RegWrite => RegWrite,
MemtoReg => MemtoReg,
RegDst => RegDst,
Sign_extend => Sign_extend,
clock => clock,
reset => reset );
* * *
That's all that's needed for the first Pipeline Register. Click here for the complete TOP_SPIM.VHD file with the first Pipeline Register. Now we need to add three more Pipeline Registers as shown in chapter 13 of "Rapid Prototyping of Digital Systems" by James O. Hamblen and Michael D. Furman.
Each Pipeline Register must have an input and output for each Signal that it delays. A new Signal is defined to connect each Pipeline Register input to the original output. Then the original Signal is connected to the corresponding Pipeline Register output. Not shown is the "reset" Signal that goes to each Pipeline Register.
John Copeland